AI Processors Shift to System-Level Design with Alchip’s 3DIC Platform

As AI processor design shifts to systems level, Alchip Technologies says its 3DIC platform is driving more efficient development of next-generation AI and high-performance computing devices through ...
EDN

Keysight elevates chiplet design environment

Chiplet PHY Designer 2025 from Keysight offers simulation capabilities for UCIe 2.0 and support for the Open Compute Project Bunch of Wires (BoW) standard. Tailored to AI and data center applications, ...
Electronic Design

Using Design-to-Test Workflows and Managing the IP Lifecycle in Chiplet Designs

1. Nilesh Kamdar addressed simulation, interoperability testing, and managing chiplet data in his presentation. Artificial intelligence (AI) has become central to EDA design optimization and debugging ...
New Electronics

Samsung Foundry and Cadence advance chiplet platform for physical AI applications

Physical AI systems, which enable machines to perceive, analyse and respond to real‑time environments, are increasingly being ...
Seeking Alpha

Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry

Expanded collaboration includes new multi-year IP agreement and joint development of advanced AI-driven flows on latest SF2P process node SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence (Nasdaq: CDNS) ...
Business Wire

Keysight Expands Chiplet Interconnect Standards Support in Chiplet PHY Designer 2025

Introduces support for the latest interconnect standards, including Universal Chiplet Interconnect Express™ (UCIe™) 2.0 and Open Compute Project Bunch of Wires (BoW). Enhances Keysight’s EDA standards ...
Semiconductor Engineering

Chiplet Standards Aim For Plug-n-Play

Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in ...
Electronic Design

Cadence Rolls Out System Chiplet to Reorganize the SoC

The semiconductor industry is moving out of the monolithic age of the system-on-chip (SoC). Instead of arranging every building block of IP on the same slab of silicon, the movers and shakers in the ...
Design And Reuse

Samsung Foundry and Cadence: Accelerating Chiplet Solutions for Physical AI

Physical AI workloads, such as real-time vision processing on a camera module, AI-enhanced radar in autonomous vehicles, smart manufacturing equipment, and sensor‑based systems, directly benefit from ...
SiliconANGLE

Baya Systems raises $36M to transform AI chiplet design

System-on-chip design startup Baya Systems Inc. said today it has closed on $36 million fuding to support its operational growth and accelerate the development of its software portfolio to meet the ...
Business Wire

Chiplet Summit Features the Latest Chip Design Technology

SAN DIEGO--(BUSINESS WIRE)--Chiplet Summit’s 2025 event offers the last word on leading-edge chip design at the Santa Clara Convention Center on January 21-23. The Tuesday tutorials cover advanced ...
Android

Apple M5 Pro & M5 Max's New Chiplet Design Could Have a Performance Benefit

Apple M5 Pro and M5 Max chips could debut at Apple’s upcoming event on March 4th and power the new MacBook Pro models. Both chips could offer more CPU and GPU cores, courtesy of a new chiplet design.