EDN

Clock domain modeling is essential in high density SoC design

Whether designing SOCs with traditional synchronous logic or alternative locally, or self-clocked “asynchronous” blocks, verification has become more important, difficult and time consuming, ...
EDN

Time Domain Modeling and Simulation of Intel QuickPath Interconnect Circuits (Part 1 of 3)

The Intel® QuickPath Interconnect operates at extremely high frequencies, so it is essential that circuit designers understand the many factors that affect differential signal integrity. This ...
CRN

Review: Can Domain-Specific Modeling Replace UML?

According to MetaCase, DSM aligns models with code at all times, even though models are not associated with any specific code language or structure. Models in DSM target specific tasks for a ...
Semiconductor Engineering

Multi-Rate Discrete-Time Modeling Approach Of A Power Hardware-in-the-Loop Setup (Karlsruhe Institute of Technology)

A technical paper titled “Multi-rate Discrete Domain Modeling of Power Hardware-in-the-Loop Setups” was published by researchers at the Institute for Technical Physics, Karlsruhe Institute of ...
Semiconductor Engineering

Turning MBSE Inside-Out For An RF EDA Shift Left

Model-based systems engineering (MBSE) focuses on creating and exploiting domain models in a digital modeling language. RF system designers trying to use generic MBSE tools soon run into a problem: ...
EDN

Time Domain Modeling and Simulation of Intel QuickPath Interconnect Circuits (Part 3 of 3)

The Intel® QuickPath Interconnect operates at extremely high frequencies, so it is essential that circuit designers understand the many factors that affect differential signal integrity. This ...